Personally I don’t suppose we are going to see the line between memory and storage be all that muddled sooner or later. Sure, 3D XPoint is a lot more responsive than Flash. But Flash isn’t all that spectacular as is. The everyday exhausting drive has entry latencies round 4ms on average. Flash can attain effectively bellow µs latency, but for very small arrays. That is costly and principally seen in Microcontrollers that execute instantly from their Flash. "Enterprise grade" flash that optimizes at cost/GB can have far greater latency, in the few to tens of µs region. 3D Xpoint is a little bit of a wash. I've seen quoted figures of sub 350ns write latency, but that is probably going for a single cell, not an array. Optane modules from Intel on the other hand have typical latencies around 5-15µs, however this is from a "system" perspective, ie, protocol and controller overhead comes into play, as well as one’s software program environment.
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DRAM on the other hand has access latencies around 2-15ns at present. The issue with latency is that it results in our processor stalling resulting from not getting the data in time. One can prefetch, but branches makes prefetching more durable, since what facet must you fetch? Branch prediction partly solves this issue. However from a efficiency standpoint, we should fetch both sides. But if we've got more latency, we have to prefetch even earlier, risking more branches. In other words, peak bandwidth required by our processor will increase at an exponential fee in comparison with latency. A charge that is software dependent as nicely. Caching might seem just like the trivial answer to the difficulty, but the efficiency of cache is proportional to the latency. To a level, cache is a magic bullet that simply makes memory latency disappear. However every time an software calls for one thing that isn’t in cache, then the appliance stalls, so long as there is threads to take its place that even have knowledge to work on, then you won’t have a efficiency deficit apart from thread switching penelties, however if you happen to don’t have such threads, then the CPU stalls.

One can be sure that more threads have their knowledge by simply making the cache greater, however cache is so much costlier than DRAM. In the long run, it all results in the fact that rising latency would require an arbitrary amount more cache for an identical system performance. Going from the few ns latency of DRAM to the couple of µs latency of current persistent memory is just not practical as an precise substitute for DRAM, even when it reduces its latency to a one centesimal it is still not impressive so far as Memory Wave goes. Though, the usage of persistent DIMMs for storage caching or as a "RAM drive" of sorts still has major benefits, but for program execution it's laughable. And i don’t suspect this to change any time soon. But I can see a future where the primary memory relocates into the CPU. The place the CPU itself has an HBM Memory Wave Audio chip or four on it supplying relatively low latency and excessive bandwidth memory to the CPU, while the exterior buses are used for IO and storage. But this isn’t all that realistic in more professional applications, since some workstation purposes honestly wants 10’s-100’s of GB of actual RAM to get good efficiency.

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